Layout Engineer

Santa Clara, (none selected)

Posted: 07/01/2019 Employment Type: Direct Hire Industry: IT Job Number: JOS000008745

Job Summary: 
You will be responsible for development and preparation of layouts and drawings of the image sensor devices from schematics and other documentation provided by engineering team(s). The work will span from definition of simple test structures/patterns, layout of arrays, to chip integration and physical verification. Occasionally you may need to prepare schematics of unit pixel, test structures/patters or array. This job will require the use of CAD tools. You will interact with other engineering teams such as Design, RnD, CAD, Tapeout and other. 
 
Responsibilities:  

  • Creating hierarchy and layout as well as schematics of the critical blocks, such as unit pixel, based on information provided from RnD team  
  • Definition, design, verification, and documentation of the blocks such as, for example, pixel arrays for both product line as well as RnD team  
  • Preparation of the floorplan and documenting layout work  
  • Support/assist in tapeout of the products and testchips  
  • Support design team with layout of critical blocks  
  • Parasitic extraction, DRC, LVS, ERC 

Requirements:  

Experience/knowledge  

  • Experience using layout tools (e.g. Cadence), techniques, and strategies as well as physical verification  
  • Experience in layout of complex blocks (mixed-signal, memory or image sensor arrays)  
  • Use of design revision control systems such as Synchronicity, Cliosoft  
  • Proven track record of delivering tasks on schedule  
  • Solid team player with excellent technical communication skills 
  • 8-10 yrs experience, Bachelors or higher degree in Electrical Engineering or related field  

Preferred Qualifications  

  • Process integration, semiconductor manufacturing, and device technology knowledge/experience  
  • Coding in Skill language, C/C++, or Perl  
  • Circuit design and simulations  
  • Image sensor experience 

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