Design Verification Engineer

San Jose, CA

Posted: 09/23/2019 Employment Type: Direct Hire Industry: Semiconductor Job Number: j-1156
Design Verification Engineer 
We are looking for a highly motivated and talented verification engineer to join our team to work on the next generation networking chips. Our product line is a fast growing business in high speed 100/200/400Gbs Ethernet and Optical Transport physical layer devices with very complex design challenges.

Job Description:
  • Architect and develop verification environment and testbench components in UVM such as BFMs and checkers.
  • Develop comprehensive test plan and implement test cases.
  • Verify design in block and chip level environment using directed and constrained random testing, assertion-based verification, formal analysis, and functional verification.
  • Perform RTL code coverage, assertion coverage, and gate level simulations.
  • Drive and adopt new verification methodologies and flows for efficiency improvements.
Job Requirements
  • MSEE/CS/CE plus 2 years, or BSEE/CS/CE plus 3 years, equivalent experience in ASIC design and verification (up to 12 yrs experience)
  • Experience in verifying designs at system level and block level.
  • Experience using SystemVerilog, VMM or UVM.
  • Familiar with System Verilog Assertions.
  • Strong experience in ASIC design verification flows and DV methodologies.
  • Networking domain knowledge preferred. (e.g. Ethernet, GFP, OTN).
  • Hands on design verification experience of gigabit Ethernet is a plus.
  • Strong and independent design debugging capability.
  • Strong programming and automated scripting language capability, e.g. C, Perl.
  • Highly motivated and be able to work both independently and as a member of team.

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