Sr. Design Verification Engineer

San Jose, CA | Direct Hire

Post Date: 12/15/2017 Job ID: 6000 Industry: Software/Hardware

Job Description/Responsibilities

As a Sr. Design Verification Engineer at our company you will be responsible for logic design verification of a variety of configurable hard and soft IP components. You will drive the definition and deployment of our verification methodology, which will include collaborating with project leads to develop verification plans, and coverage analysis.

 

 

 

Primary Responsibilities:

Leading the definition and deployment of verification methodology.

  • Functional verification of embedded FPGA components such as BRAMs, DSP blocks, etc.
  • Development and integration of verification IP.
  • Evaluating and acquiring third-party verification IP, as needed.
  • Testbench development in SystemVerilog targeting complete coverage
  • Support of SystemVerilog assertion and coverage-driven methodology
  • Developing Behavioral models of Achronix IP blocks.
  • Support of design verification methodology enhancements

Experience:

  • 5+ years of SoC/ASIC verification experience
  • Experience developing verification environments.
  • Experience with UVM, or other constrained random verification environments.
  • Experience using 3rd party verification IP.
  • Experience with AMBA interfaces.
  • Experience with of programming language such as C++
  • Experience with of scripting language such as TCL and Python.

Education:

  • Bachelor’s degree in Electrical or Computer Engineering or equivalent

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