SR. DFT Engineer

San Jose, CA | Direct Hire

Post Date: 11/01/2017 Job ID: 6023 Industry: Semiconductor

Job Description/Responsibilities

The employee will work on the design, implementation, testability, and characterization of full-custom, high-performance digital logic in 14nm/16nm and below.  The employee will work as a design-for-test (DFT) lead for the FPGAs’ reconfigurable logic fabric. His/her responsibilities will include the following:

  • Own the top-level DFT strategy of future products, including design of dedicated DFT hardware and overall flow definition
  • Collaborate with other members of the team to ensure DFT structures integrate seamlessly with existing hardware
  • Develop test methodologies and guidelines for each process node
  • Work closely with foundry employees on process development, customer support, EDA, reliability, test, and product qualification
  • Develop automated processes for pattern generation
  • Define product specifications as related to DFT
  • Work closely with test engineers and customers to implement system boards, load boards, and ATE setup


kills and Qualifications

  • Experience with industry-standard fault/coverage models
  • Experience with DFT tools and methodologies for both ASICs and FPGAs
  • Experience using industry-standard test equipment
  • Experience reading and writing RTL (e.g., Verilog)
  • Experience with commercial CAD flows related to DFT
  • Comfortable programming in a scripting language (e.g., Python or Perl) and writing full programs from scratch (e.g., 5000+ lines of code)
  • Comfortable designing/maintaining flows and methodologies from scratch
  • Familiarity with object-oriented programming concepts is a plus
  • Familiarity with revision-control systems (e.g., perforce, git) is a plus
  • Familiarity with using and/or designing FPGAs is a plus
  • Excellent debugging skills
  • Well organized, punctual, and excellent communication skills
  • BS/MS in electrical engineering or computer science +5-15 years experience

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