Principal Engineer/Design Verification Lead

(none selected) | Direct Hire

Post Date: 07/17/2017 Job ID: JOS000006874 Industry: Software/Hardware

- Principal Engineer/Design Verification Lead, 10+ years of experience (BS/MS required. MS preferred)
- Can independently architect, design and develop a verification environment using OOP from scratch
- Should be able to create constraint random environment with functional coverage
- Should be an expert at understanding digital design documents, protocol specification and be able to create a test plan
- Solid written and communication skills, be able to lead others to get timely execution
- PCIe domain knowledge expected but not required
- Prior UVM/VMM experience must. SystemVerilog, Verilog, C background expected.
- Coverage closure, design debug, defect triaging skills are key
- Be able to mentor, lead, perform conflict resolution
 


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