Principal Electrical Engineers

East Bay, (none selected) | Direct Hire

Post Date: 06/07/2016 Job ID: 6023 Industry: Manufacturing

  The ideal candidate for this position has broad expertise across multiple IO protocols and standards, including memory interfaces (DDR3/4, LPDDR*, SSRAM, QDR, RLDRAM, flash, etc), system interfaces (e.g. cpu busses, AXI*)  and non-SerDes network-oriented interfaces (SGMII, RGMII, S3MII, GMII etc.), with a detailed understanding of how the requirements imposed by these standards define the architecture and implementation of the PHYs.
-         The emphasis will be on the network-oriented interfaces.
-         Knowledge about electrical IO standards is important: LVDS, SSTL, HSTL, etc.,
-         Similarly, expertise with SI and design for low jitter is important.
-         Affinity with analog design of programmable IOs, PLLs, DLLs, PVT compensation features etc. is a definite plus.
-         The ideal candidate has worked on architecting such interfaces for several years, most likely in FPGA companies like Xilinx, Altera, Lattice or Microsemi/Actel.  Candidates whose background includes network equipment makers like Cisco, Juniper, Brocade etc. may also be a good fit.
-         Required skills:  Verilog, SDC (timing constraints), simulators (e.g. VCS, Modelsim), formal verification tools, scripting languages.
-         Fluency in Mandarin is a plus.

e are looking to add 1-3 senior/principal design engineers to design high speed digital logic for programmable IO structures on our new products 16nm/14nm/10nm/7nm
Designer should have experience designing, verification and testing high speed digital logic for advanced CMOS technologies 20mm, 16nm etc.
Experience at Altera, Xilinx, Lattice, etc would be ideal in hardware design team. FPAG design experience required.
Candidates could also be working on SOC/ASIC design at ASSP companies e.g. Broadcom, Avago, marvell etc
Experience designing DDR3 logic controllers (Phy), 10G Ethernet, PCI Express would be useful. NOT interested in analog buffer designers or SerDes designers. 
Understanding of IO system level protocols an advantage: DDR, PCI, 10G Ethernet, CPU buses, AXI, QPI, HBM etc
The search must be kept confidential, as there is a high concentration at one company, for example, and we do not want the outside world to know that we are recruiting these positions.

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