HW Engineering Manager

San Jose, CA | Direct Hire

Post Date: 11/01/2017 Job ID: 6027 Industry: Semiconductor

 

The Core Technology team at our company owns the reconfigurable “fabric” (look-up tables, routing, configuration memory, carry chains, register files, multipliers, etc.) for our company’s FPGAs. Members of our team participate in all phases of the FPGA product-development cycle, from architecture conception to circuit design and implementation to high-volume manufacturing. New employees will have the opportunity to contribute to all of these phases and work with the world’s most advanced process technology.

Position Profile Name: Hardware Engineer Manager, Core Technology

Type of Position: Regular, Exempt

Reports to: Vice President of Hardware Engineering

Location: Santa Clara, CA


Job Description and Responsibilities

The employee will work on the design, implementation, and characterization of full-custom, high-performance digital logic in 14nm/16nm and below. The employee will work as a design lead on multiple blocks in our FPGAs’ reconfigurable logic fabric. His or her responsibilities will include the following:

- Manage a team (5-10 people) of hardware engineers tasked with the design and implementation of a fully custom FPGA fabric

- Own the design of full-custom and RTL-based digital logic blocks

- Collaborate with team members to optimize physical design and verification methodologies

- Estimate the power, performance, and area of the custom and RTL blocks both before and after physical implementation

- Develop design methodologies and guidelines for each process node

- Work closely with foundry employees on process development, customer support, EDA, reliability, test, and product qualification

- Develop automated processes for block-level and system-level verification

 

Skills and Qualifications:

- Experience managing a team of hardware engineers

- Experience with digital VLSI design

- Experience developing custom digital logic, defining layout conventions (e.g. track plans, cell grids), and defining CAD methodologies (e.g. DRC/LVS/extraction settings) in advanced process nodes (14/16nm, 10nm)

- Experience reading and writing RTL (e.g., Verilog)

- Experience running SPICE simulations

- Experience with commercial CAD flows (LVS, DRC, simulation, etc.)

- Comfortable programming in a scripting language (e.g., Python or Perl) and writing full programs from scratch (e.g. 5000+ lines of code)

- Comfortable designing/maintaining flows and methodologies from scratch

- Familiarity with object-oriented programming concepts is a plus

- Familiarity with revision-control systems (e.g., perforce, git) is a plus

- Familiarity with using and/or designing FPGAs is a plus

- Familiarity with hardware protocols such as Ethernet, PCIe, & DDR3/4 is a plus

- Excellent debugging skills

- Well organized, punctual, and excellent communication skills

- BS/MS in electrical engineering or computer science +10-20 years experience


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