HW Engineer - Timing Flow

San Jose, CA | Direct Hire

Post Date: 09/29/2017 Job ID: 6003 Industry: Software/Hardware
Position Profile Name: [Staff/Senior] Hardware Engineer – Timing Flow, Core Technology
Requisition No.: 6200-1005
Type of Position: Regular, Exempt
Reports to: Hardware Engineering Manager, Core Technology
Location: Santa Clara, California
Contact: hr@achronix.com

Job Description/Responsibilities

The employee will work on the design, implementation, and characterization of full-custom, high-performance digital logic in 14nm/16nm and below.  The employee will share responsibilities across design and verification, but focus on timing characterization.  His or her responsibilities will include the following:

  • Own timing flows and methodologies for the full-custom portion of an FPGA
  • Develop and maintain automated scripts to extract timing values from SPICE netlists, convert to an internal database format, and deliver to other teams.
  • Collaborate with other members of the team to optimize our physical design and verification methodologies
  • Estimate the power, performance, and area of the custom and RTL blocks both before and after physical implementation
  • Develop design methodologies and guidelines for each process node
  • Work closely with foundry employees on process development, customer support, EDA, reliability, test, and product qualification
  • Develop automated processes for block-level and system-level verification
  • Mentor junior engineers

 

Skills and Qualifications:

  • Experience programming in a scripting language (e.g., Python or Perl) and writing full programs from scratch (e.g. 5000+ lines of code)
  • Experience designing/maintaining flows and methodologies from scratch
  • Experience with digital VLSI design
  • Experience reading and writing RTL (e.g., Verilog)
  • Experience running SPICE simulations
  • Experience with commercial CAD flows (LVS, DRC, simulation,)
  • Experience developing digital logic, defining layout conventions (e.g. track plans, cell grids), and defining CAD methodologies (e.g. DRC/LVS/extraction settings) in advanced process nodes (14/16nm, 10nm)
  • Familiarity with object-oriented programming concepts is a plus
  • Familiarity with revision-control systems (e.g., perforce, git) is a plus
  • Familiarity with using and/or designing FPGAs is a plus
  • Familiarity with hardware protocols such as Ethernet, PCIe, & DDR3/4 is a plus
  • Excellent debugging skills
  • Well organized, punctual, and excellent communication skills
  • BS/MS in electrical engineering or computer science +2-10 years experience

 


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